The present invention relates to a semiconductor integrated circuit device and to technology for producing the same. More particularly, it relates to techniques which are effective when applied to a semiconductor integrated circuit device having a logic (logic circuit)/memory hybrid type memory wherein a memory circuit and a logic circuit are fabricated on an identical semiconductor substrate, and to technology for producing the semiconductor integrated circuit device.
In recent years, logic/memory hybrid type memories in which a DRAM (Dynamic Random Access Memory) and a logic circuit are fabricated on an identical semiconductor substrate have been developed and produced.
Each memory cell of the DRAM includes one MIS (Metal-Insulator-Semiconductor) transistor for selecting the memory cell, and one capacitor connected in series with the MIS transistor. Herein, the capacitor is employed as an element in which information is stored. Accordingly, when the capacitor is allowed to stand, signal charges for storing the information leak with the lapse of time until the stored data is lost.
In the DRAM, therefore, a so-called xe2x80x9crefresh operationxe2x80x9d is required, in which the stored content is cyclically refreshed for retaining the information stored in the memory cell. With enhancement in the operating speed of the overall DRAM, various researches and technical developments have been made on the structure and circuit arrangement of the DRAM in order to enhance the refresh characteristics.
It is also a problem of the DRAM to heighten the threshold voltage Vth of the memory cell selecting MIS transistor. It is disclosed in the official gazette of Japanese Patent Application Laid-open No. 214155/1990, No. 58556/1992 or No. 36318/1997 that, as a practicable expedient for solving this problem, polycrystalline silicon whose conductivity type is the p-type is employed for the gate electrode of a MIS transistor of n-channel type.
A MIS transistor for selecting a memory cell is a switching element, which is interposed between a capacitor and a bit line, and which serves to electrically connect and disconnect them. It includes a pair of semiconductor regions for a source and a drain which are formed in a semiconductor substrate, and a gate electrode which is formed on the semiconductor substrate through a gate insulating film.
An active region, in which the memory cell selecting MIS transistor is formed, is defined by an element isolation region. LOCOS (Local Oxidation of Silicon) is usually applied to the element isolation region for the reasons of easy formation, etc.
However, an impurity region for preventing inversion is required at the boundary between the LOCOS region and the semiconductor substrate. More specifically, the impurity region, which has the same conductivity type as that of the semiconductor substrate and which has a high impurity concentration, is formed in the part of the semiconductor substrate underlying the LOCOS region.
As a consequence, an electric field intensified at the junction between the impurity region and the semiconductor region of the storage node of the memory cell selecting MIS transistor, resulting on the problem that the refresh characteristics of the memory cell are deteriorated.
Besides, in a logic/memory hybrid type DRAM, a DRAM circuit and a logic circuit are unified to facilitate the producing process. By way of example, the gate insulating films of the memory cell selecting MIS transistors of the DRAM circuit and those of the MIS transistors of the logic circuit are formed at the same time. Since, however, a high voltage is required in boosting the potential of a word line, the gate insulating film cannot be made very thin in the memory cell selecting MIS transistor from the viewpoint of ensuring reliability. In consequence, the gate insulating film of the MIS transistor of the logic circuit must be thickened in agreement with the gate insulating film of the memory cell selecting MIS transistor. This results in the further problem that, in the MIS transistor of the logic circuit, the gate insulating film becomes unnecessarily thick, thereby to hamper enhancements in various capabilities, such as the driving current.
An object of the present invention is to provide a technique which can enhance refresh characteristics in a semiconductor integrated circuit device having a logic/memory hybrid type memory.
Another object of the present invention is to provide a technique which can enhance the driving capability of each MIS transistor of a logic circuit in a semiconductor integrated circuit device having a logic/memory hybrid type memory.
The above and other objects and novel features of the present invention will become apparent from the description provided in this specification when read in conjunction with the accompanying drawings.
Typical aspects of performance of the present invention are briefly summarized as follows:
A semiconductor integrated circuit device according to the present invention comprises a semiconductor integrated circuit device having a memory cell in which a MIS transistor and a capacitance element are connected in series, on a semiconductor substrate, wherein said MIS transistor includes a gate electrode in which polycrystalline silicon is disposed in contact with a gate insulating film, the conductivity type of said polycrystalline silicon is opposite to that of the semiconductor region for the source and drain regions of said MIS transistor, and an element isolation region for defining an active region of a semiconductor substrate, in which said MIS transistor is formed, is formed by burying an insulating film in an isolation groove which is formed in said semiconductor substrate.
Besides, a semiconductor integrated circuit device according to the present invention is characterized in that a logic circuit is formed around said memory cell, and that the conductivity type of a gate electrode of a MIS transistor, which constitutes said logic circuit, is identical to that of the semiconductor regions for a source and a drain of the logic-circuit constituting the MIS transistor.
Further, a semiconductor integrated circuit device according to the present invention is characterized in that the thickness of the gate insulating film of said MIS transistor of said memory cell is relatively greater than that of a gate insulating film of a MIS transistor which constitutes said logic circuit.
On the other hand, a method of producing a semiconductor integrated circuit device according to the present invention is characterized in that a memory cell in which a MIS transistor and a capacitance element are connected in series is formed on a semiconductor substrate, the method comprising the steps of:
(a) forming an isolation groove in a principal surface of the semiconductor substrate, and thereafter burying an insulating film in said isolation groove, thereby to form an isolation region;
(b) forming a gate insulating film on the resultant semiconductor substrate;
(c) depositing a polycrystalline silicon film on said gate insulating film; and
(d) introducing an impurity into a gate electrode forming region for the MIS transistor within said polycrystalline silicon film, said impurity having a conductivity type opposite to that of the semiconductor regions for a source and a drain of said MIS transistor, wherein at the step of introducing said impurity into said gate electrode forming region within said polycrystalline silicon film, said impurity is simultaneously introduced into a gate electrode forming region for a MIS transistor other than the memory cell selecting MIS transistor, within said polycrystalline silicon film.